1. Field of the Invention
The present invention relates to a semiconductor design technology; and, more particularly, to a one-time programmable (OTP) unit cell using a CMOS gate-oxide antifuse and a nonvolatile memory device with the same.
2. Description of Related Art
One-time programmable (OTP) unit cells using an antifuse formed by a gate oxide layer of a complementary metal-oxide-semiconductor (CMOS) (Hereinafter, referring to as “a CMOS gate-oxide antifuse”) are formed inside a volatile memory device such as Dynamic Random-Access-Memory (DRAM) or a nonvolatile memory device, such as an Electrically Erasable Programmable Read-Only-Memory (EEPROM) or a flash memory, and are used for memory repair purpose. In addition, the OTP unit cells are used for internal operating voltage and frequency trimming in a mixed-signal chip where an analog chip and a digital chip are mixed.
Generally, each OTP unit cell includes a CMOS gate-oxide antifuse and one or more MOS transistors. Such an OTP unit cell is formed inside each memory chip in a single or array configuration and is used for repair or trimming.
FIG. 1 is an equivalent circuit diagram of a typical OTP unit cell.
Referring to FIG. 1, the typical OTP unit cell includes an antifuse ANT_FS1 and transistors NM1 and NM2. The antifuse ANT_FS1 is connected between an input node A and a node B. The transistors NM1 and NM2 are n-channel transistors, and are connected in series between the node B and an output node E which is a terminal through which data are outputted during a read operation.
The typical OTP unit cell has to include the transistors NM1 and NM2 connected in series for forming a current path from the input node A to the output node E during the read operation. Accordingly, a final data is outputted from the output node E with a state that its voltage is dropped by a total amount of threshold voltages of the transistors NM1 and NM2, i.e., VDD−2*Vt, ‘Vt’ denoting the threshold voltage of each transistor NM1 and NM2. As a result, since a sensing margin of data outputted from the output node E becomes narrower, a malfunction occurs during the read operation, which degrades the reliability in the read operation of the OTP unit cell.
In FIG. 1, each of reference symbols ‘C’ and ‘D’ denotes an input node receiving control signals.
To improve performance of the typical OTP unit cell shown in FIG. 1, an OTP unit cell having a new structure is disclosed in a commonly owned copending application, KR Registration No. 10-0845407 issued on Jul. 3, 2008, and filed on Feb. 16, 2007, entitled “ONE-TIME-PROGRAMMABLE CELL AND MEMORY DEVICE HAVING THE SAME”.
FIG. 2 is an equivalent circuit diagram of an OTP unit cell proposed in a Korean Patent application, KR Registration No. 10-0845407.
Referring to FIG. 2, the OTP unit cell includes an antifuse ANT_FS2, and first and second transistors PM1 and PM2 to output a voltage at a third node N3 as an output signal. The antifuse ANT_FS2 is coupled between the third node N3 and a ground voltage terminal. The first transistor PM1 has a gate receiving a write control signal WR CTRL and a source-drain path between the third node N3 and a second node N2. The second transistor PM2 has a gate receiving a read control signal RD_CTRL and a source-drain path between a first node N1 and the third node N3. The OTP unit cell further includes a sensing amplifier 100 of an inverter type for sensing and amplifying the output signal.
In the OTP unit cell shown in FIG. 2, a write voltage and a read voltage are applied to the antifuse ANT_FS2 through different paths from each other since the antifuse ANT_FS2 and the first and second transistors PM1 and PM2 are coupled in parallel. Accordingly, loss of the read voltage during a read operation can be minimized in comparison with the OTP unit cell shown in FIG. 1, and thus, a sensing margin of data outputted from the OTP unit cell becomes broader to thereby improve the reliability in the read operation of the OTP unit cell.
As described above, the OTP unit cell shown in FIG. 2 can improve the reliability in the read operation in comparison with the OTP unit cell shown in FIG. 1. However, since the OTP unit cell shown in FIG. 2 includes one antifuse and two transistors like the OTP unit cell shown in FIG. 1, there is limitation to reduce a size and thus power consumption increases.